1. Field of the Invention
The present disclosure relates to a liquid crystal display device and, more particularly, to a circuit for driving a liquid crystal display device, which is capable of reducing the number of writing processes performed by an operator and reducing a space of a programmable power integrated circuit (PPIC) so as to reduce costs, by storing PPIC voltage setting data in a memory, reading the voltage setting data stored in the memory by a timing controller when a voltage is applied, and transmitting the voltage setting data to the PPIC so as to set a voltage.
2. Discussion of the Related Art
Recently, among display devices, flat panel displays have been widely used as display devices due to their excellent image quality, light weight, slimness and low power consumption. As the flat panel display, a Liquid Crystal Display (LCD) device, an Organic Light Emitting Diode (OLED) display device, etc. have been commercially used.
An LCD device displays an image using electrical and optical characteristics of liquid crystal. Liquid crystal has an anisotropic property in which a refractive index and a dielectric constant are changed according to major-axis direction and minor-axis direction of molecular and may easily adjust molecule arrangement and optical characteristics. The LCD device using liquid crystal displays an image by changing an arrangement direction of liquid crystal molecules according to the magnitude of an electric field so as to adjust transmittance of light passing through a polarization plate.
The general LCD device will now be described with reference to the accompanying drawings.
FIG. 1 is a diagram showing the configuration of a general LCD device, FIG. 2 is a diagram showing the configuration of a general EEPROM, and FIG. 3 is a diagram showing the configuration of a general programmable power IC (PPIC).
As shown in FIG. 1, the general LCD device includes a liquid crystal panel 2 including a plurality of gate lines GL1 to GLn arranged in one direction at a predetermined interval, a plurality of data lines DL1 to DLm arranged in a direction perpendicular to the plurality of gate lines GL1 to GLn to define pixel regions, thin film transistors (TFTs) respectively formed in the pixel regions and liquid crystal capacitors Clc connected to the TFTs; a gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2; a data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; a timing controller 8 for aligning image data RGB received from an external system 1, supplying the aligned image data RGB to the data driver 4, and controlling the data driver 4; an Electrically Erasable Programmable Read-Only Memory (EEPROM) 9 for storing data necessary for operation of the timing controller 8; a power supply 10 for receiving power from the external system 1 and supplying power to each unit; and a programmable power IC (PPIC) 11 for storing voltage setting data for supplying a reference voltage Vref and a common voltage Vcom to the data driver 4 according to model.
The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT and a common electrode provided on the pixel electrode with liquid crystal interposed therebetween. The TFT supplies an image signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges a difference voltage between the image signal supplied to the pixel electrode and the common voltage and changes arrangement of liquid crystal molecules according to the difference voltage to control light transmittance, thereby implementing gray scale. At this time, a storage capacitor Cst may be formed by stacking the pixel electrode and a storage line with an insulating film interposed therebetween.
The gate driver 6 sequentially drives the gate lines GL1 to GLn according to a gate control signal (GCS) from the timing controller 8. More specifically, the gate driver 4 sequentially supplies a scan pulse of a gate high voltage (VGH) level to each of the gate lines GL1 to GLn using a gate start pulse (GSP), a gate shift clock (GSC) and a gate output enable (GOE) signal, all of which are gate control signals (GCS). In the remaining period in which the scan pulse is not supplied, a gate low voltage is supplied.
The data driver 4 receives the aligned data from the timing controller 8, receives the voltage from the PPIC and converts the voltage into an analog voltage, that is, an image signal, using a data control signal (DCS) from the timing controller 8, such as a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE) signal and an inversion (Pol) signal.
The timing controller 8 controls the data driver 4 and the gate driver 6 according to external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync and DE. More specifically, the timing controller 8 aligns the external image data RGB according to driving of the liquid crystal panel 2 and supplies the aligned image data to the data driver 4. The timing controller generates the gate control signal (GCS) and the data control signal (DCS) using at least one of the external synchronization signals, that is, a dot clock DCLK, a data enable signal DE, horizontal and vertical synchronization signals Hsync and Vsync, and supplies the same to the gate driver 6 and the data driver 4.
The timing controller 8 for performing the above operation uses the EEPROM 9 located outside a chip in order to store target register configuration data for controlling the above operation.
That is, data corresponding to an LCD device of each model is written in the EEPROM 9 shown in FIG. 2 and the timing controller 8 reads and uses necessary data from the EEPROM 9. A separate memory for storing the voltage setting data is included in the PPIC 11 shown in FIG. 3 and the PPIC 11 outputs a voltage according to the voltage setting data stored in the internal memory regardless of control of the timing controller 8 when power is applied. That is, a logic for physical communication and signal processing is not present between the timing controller 8 and the PPIC 11.
However, the conventional circuit for driving the LCD device has the following problems.
That is, the EEPROM has a data storage function and a function for exchanging data through communication with the timing controller. The PPIC has a communication function for voltage programming and a data storage function. However, since data is separately written, a data writing process is performed two times. Thus, much processing time is consumed. In addition, since spaces for the EEPROM and the PPIC should be secured, costs are increased.